1. Field of the Invention
The present invention relates to a semiconductor device, and more specifically to a structure of an interlayer insulator film in a semiconductor device, and a method for planarizing an interlayer insulator film in a semiconductor device.
2. Description of Related Art
With an elevated integration density of semiconductor devices, a three-dimensional structure of an integrated circuit is becoming complicated more and more, and on the other hand, a demand for the degree of flatness in an interlayer insulator film formed on a circuit pattern is becoming severe more and more because it is required for a lithography. In the prior art, the most conventional planarization method is a so-called reflow process in that an interlayer insulator film is formed of BPSG (borophosphosilicate glass, namely, silicon oxide added with impurities of phosphorus (P) and boron (B)), and a heat treatment is conducted at a temperature not less than a melting point so as to cause the interlayer insulator film to be planarized by action of fluidization caused by a surface tension. This is a very simple method.
Furthermore, although the planarization was realized by a single layer of BPSG, a so-called two-layer planarization process is recently used because of a further elevated degree of flatness required in the most advanced semiconductor devices. For example, after the reflow of the BPSG film, a SOG (spin on glass) film is deposited, and the whole surface is etched back by a dry etching, for the purpose of further elevating the degree of flatness.
Referring to FIG. 1A to 1C, there are shown diagrammatic sectional views of a semiconductor device for illustrating one example of the prior art two-layer planarization process.
As shown in FIG. 1A, a gate oxide film 2 and a circuit pattern 3, formed of for example a polysilicon film, are formed on a principal surface of a semiconductor substrate 1, and a BPSG having a phosphorus concentration of 3 mol % to 6 mol % and a boron concentration of 8 mol % to 15 mol % is deposited by means of a CVD (chemical vapor deposition) process, to form an interlayer film 4 having a desired thickness and covering the circuit pattern 3 and the gate oxide film 2, and then, a heat treatment is conducted at a temperature of 750.degree. C. to 900.degree. C. to cause the reflow of the deposited BPSG film 4.
Then, as shown in FIG. 1B, an SOG film 6 is formed to cover the BPSG film 4, by a spin coating and a succeeding baking at 300.degree. C. to 400.degree. C. Thereafter, as shown in FIG. 1C, a whole surface etchback is carried out by use of a dry etching. Thus, a planarization is completed.
In the process as mentioned above, because of viscous fluidization of the SOG film, the film thickness of the SOG film in an area excluding the circuit pattern becomes larger than the film thickness of the SOG film on the circuit pattern. As a result, the degree of flatness is further elevated as a matter of course, in comparison with the reflow of the single layer of BPSG film.
Furthermore, in the case of not capable of executing the heat treatment at a high temperature of not less than 750.degree. C., as in the case that an interlayer insulator film is formed on the semiconductor substrate having a wiring conductor formed of a non-refractory metal such as aluminum, it is possible to utilize a process proposed by Japanese Patent Application Pre-examination Publication Nos. JP-A-4-165651 and JP-A-5-267283. In this process, an interlayer insulator film is formed by depositing a silicon oxide film by use of a plasma CVD process (PE(plasma enhanced)-SiO film), and similarly to the first mentioned two-layer planarization process, an SOG film is deposited by a spin coating and a succeeding baking at 300.degree. C. to 400.degree. C., and then, a whole surface etchback is carried out by use of a dry etching.
Alternatively, for the purpose of seeking an elevated flatness, a etchback process using a chemical mechanical polishing (CMP) becomes gradually widely used. This CMP process makes it possible to obtain an excellent flatness, depending upon an underlying layer shape at some degree.
In addition, Japanese Patent Application Pre-examination Publication Nos. JP-A-5-055391 proposes a process for forming an SOG film by means of a plurality of executions of the spin coating, in order to elevate the degree of flatness, and Japanese Patent Application Pre-examination Publication Nos. JP-A-4-359544 proposes a process in which a lithography is executed to the effect that, after an SOG film is deposited and baked, the SOG film is intentionally left on an interlayer insulator film in a recess portion, namely, in an area excluding a circuit pattern, for the purpose of elevating the degree of flatness.
However, the above mentioned various prior art planarization processes of the interlayer insulator film have the following disadvantages: First, a large three-dimensional step still remains even after the etchback process is executed, since a selective etching ratio between the SOG film and the underlying BPSG film or PE-SiO film is not sufficient. In brief, the selective etching ratio between the SOG film and the BPSG film or PE-SiO film is limited to 1.6 to 2.0. For example, assuming that there is a large three-dimensional step of 1 .mu.m before formation of the interlayer insulator film, since only 10% to 30% of the step can planarized by the prior art planarization processes, the three-dimensional step of not less than 0.7 .mu.m remains even after the formation of the interlayer insulator film.
In the most advanced DRAM (dynamic random access memory), a capacitor has recently become remarkably large in size because of a necessity of ensuring a capacitor plate area, and a satisfactory degree of flatness can be no longer obtained by the prior art planarization processes.
Secondly, the CMP process is satisfactory to compensate for the flatness property so as to obtain a desired degree of flatness, but a throughput is low and a running cost is high so that a production efficiency drops as a whole. In the CMP process, in addition, a substrate to be etched back is desired to be as flat as possible. Therefore, when the CMP process is applied to a semiconductor device having many concaves and convexes such as a DRAM, it is difficult to ensure a uniform etching rate, with the result that the advantage of the CMP process can be sufficiently enjoyed. In a semiconductor device such as DRAM which is low in an added value, it is important to inexpensively and quickly produce semiconductor device chips. In this aspect, the CMP process is not suitable in practice. In other words, the CMP process has many problems to be solved.